1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the fabrication of highly sophisticated field effect transistors, such as MOS transistor structures in SOI configuration, requiring highly doped shallow junctions and reduced series resistance.
2. Description of the Related Art
The manufacturing process for integrated circuits continues to improve in several ways, driven by the ongoing efforts to scale down the feature sizes of the individual circuit elements. Presently, and in the foreseeable future, the majority of integrated circuits are, and will be, based on silicon devices, due to the high availability of silicon substrates and due to the well-established process technology that has been developed over the past decades. A key issue in developing integrated circuits of increased packing density and enhanced performance is the scaling of transistor elements, such as MOS transistor elements, to provide the great number of transistor elements that may be necessary for producing modern CPUs and memory devices. One important aspect in manufacturing field effect transistors having reduced dimensions is the reduction of the length of the gate electrode that controls the formation of a conductive channel separating the source and drain regions of the transistor. The source and drain regions of the transistor element are conductive semiconductor regions including dopants of an inverse conductivity type compared to the dopants in the surrounding crystalline active region, e.g., a substrate or a well region.
Although the reduction of the gate length is necessary for obtaining smaller and faster transistor elements, it turns out, however, that a plurality of issues are additionally involved to maintain proper transistor performance for a reduced gate length. One challenging task in this respect is the provision of shallow junction regions, at least at the area in the vicinity of the channel region, i.e., source and drain extension regions, which nevertheless exhibit a high conductivity to minimize the resistivity in conducting charge carriers from the channel to a respective contact area of the drain and source regions. The requirement for shallow junctions having a high conductivity is commonly met by performing an ion implantation sequence to obtain a high dopant concentration having a profile that varies laterally and in depth. The introduction of a high dose of dopants into a crystalline substrate area, however, generates heavy damage in the crystal structure, and therefore one or more anneal cycles are typically required for activating the dopants, i.e., for placing the dopants at crystal sites, and to cure the heavy crystal damage. However, the electrically effective dopant concentration is limited by the ability of the anneal cycles to electrically activate the dopants. This ability in turn is limited by the solid solubility of the dopants in the silicon crystal and the temperature and duration of the anneal process that are compatible with the process requirements. Moreover, besides the dopant activation and the curing of crystal damage, dopant diffusion may also occur during the annealing, which may lead to a “blurring” of the dopant profile, which may be advantageous for defining critical transistor properties, such as the overlap between the extension regions and the gate electrode. In other areas of the drain and source regions, that is, in deeper lying portions, the diffusion may result in a reduction of the dopant concentration at the corresponding PN junction areas, thereby reducing the conductivity at the vicinity of theses areas.
Thus, on the one hand, a high anneal temperature may be desirable in view of a high degree of dopant activation, re-crystallization of implantation-induced lattice damage and a desired diffusion at shallow areas of the extension regions, while, on the other hand, the duration of the anneal process should be short in order to restrict the degree of dopant diffusion in the deeper drain and source regions, which may reduce the dopant gradient at the respective PN junctions and also reduce the overall conductivity due to reducing the averaged dopant concentration. Furthermore, very high temperatures during the anneal process may negatively affect the gate insulation layer, thereby reducing the reliability thereof. That is, high anneal temperatures may degrade the gate insulation layer and thus may influence the dielectric characteristics thereof, which may result in increased leakage currents, reduced breakdown voltage and the like. Therefore, for highly advanced transistors, the positioning, shaping and maintaining of a desired dopant profile are important properties for defining the final performance of the device, since the overall series resistance of the conductive path between the drain and source contacts may represent a dominant part for determining the transistor performance.
Recently, advanced anneal techniques have been developed in which extremely high temperatures may be achieved at a surface portion of the substrate, thereby providing sufficient energy to the atoms for activating the dopants and re-crystallizing lattice damage, wherein, however, the duration of the treatment is short enough to substantially prevent a significant diffusion of the dopant species and other impurities contained in the carrier material. Respective advanced anneal techniques are typically performed on the basis of radiation sources that are configured to provide light of appropriate wavelength that may be efficiently absorbed in upper portions of the substrate and any components formed thereon, wherein the effective duration of the irradiation may be controlled to a desired small time interval, such as a few milliseconds and significantly less. For instance, respective flash lamp exposure sources are available which provide light of a defined wavelength range resulting in a surface-near heating of material, thereby providing the conditions for short range motions of the respective atoms in the materials provided near the surface of the carrier material. In other cases, laser radiation may be used, for instance, in the form of short laser pulses or a continuous beam that may be scanned across the substrate surface on the basis of an appropriate scan regime in order to obtain the desired short term heating at each point on the substrate. Thus, contrary to traditional rapid thermal anneal (RTA) processes, in which frequently the entire carrier material may be heated to a desired temperature, the radiation-based advanced anneal techniques cause non-equilibrium conditions wherein a high amount of power is supplied within extremely short time intervals, thereby providing the required extremely high temperatures at a very thin surface layer, while the remaining material of the substrate may remain substantially unaffected by the energy deposition during the anneal process. Thus, in advanced manufacturing regimes, traditional RTA processes may frequently be replaced by advanced radiation-based anneal processes in order to obtain a high degree of dopant activation and re-crystallization in drain and source regions while not unduly contributing to dopant diffusion, which may be advantageous in terms of a steep dopant gradient at the respective PN junctions. However, adjusting the effective channel length on the basis of a well-controlled diffusion of the dopants may be difficult to be integrated in the conventional process flow unless significant efforts may have to be made, thereby resulting in additional process complexity. On the other hand, the definition of the effective channel length on the basis of conventional well-established anneal techniques may require an increased spacer width and thus increased lateral dimensions of the transistor, when an efficient process flow is to be maintained, as will be explained in more detail with reference to FIGS. 1a-1c. 
FIG. 1a schematically illustrates a cross-sectional view of a transistor device 100 in an advanced manufacturing stage. The transistor 100 may represent any type of sophisticated field effect transistor as typically used in sophisticated integrated circuits, such as microprocessors, storage chips and the like. The transistor 100 comprises a substrate 101, which may represent any appropriate carrier material for forming thereon an insulating layer 103 and an appropriate semiconductor layer 102, in and above which respective circuit components, such as the transistor 100, are to be formed. For example, the substrate 101 may represent a silicon substrate or any other appropriate material, thereby defining a silicon-on-insulator (SOI) configuration. Furthermore, a gate electrode 105, for instance comprised of polysilicon, may be formed above the semiconductor layer 102 and may be separated therefrom by a gate insulation layer 104. In this manufacturing stage, respective offset spacers 107, which may be comprised of silicon dioxide, silicon oxynitride and the like, are provided with an appropriate thickness 107T, which in turn is selected so as to define a desired offset of respective extension regions 108E defined by a corresponding dopant species of a specified conductivity type in accordance with the design of the transistor device 100. For instance, for an N-channel transistor, the extension regions 108 may comprise an N-type dopant species. Furthermore, the crystalline structure of the semiconductor layer 102 adjacent to the gate electrode 105 may be damaged or substantially amorphized, thereby defining a respective substantially amorphous region 109, which may result in enhanced isotropy during the formation of the extension regions 108 and further implantation processes, as will be described later on.
It should be appreciated that the length of a channel region 106, i.e., in FIG. 1a, the spacing between the extension regions 108E in the horizontal direction, depends on the length of the gate electrode 105 wherein the actual effective channel length may finally be determined by respective PN junctions formed by the extension regions 108E with the channel region 106. That is, the effective channel length may be adjusted by a controlled diffusion process, as previously explained, wherein the overall lateral dimensions in the transistor length direction may also be affected by this process strategy, as will be explained later on.
The transistor device 100 as shown in FIG. 1a may be formed on the basis of the following well-established processes. After providing the substrate 101 having formed thereon the buried insulating layer 103 and the semiconductor layer 102, respective isolation structures (not shown), such as shallow trench isolations (STI) and the like, may be formed to define appropriately sized active areas within the semiconductor layer 102, in which one or more circuit components may be formed, such as the transistor 100. For this purpose, sophisticated lithography, etch, deposition and planarization techniques may be used. Subsequently, the doping of the channel region 106 may be adjusted in accordance with transistor requirements. Thereafter, appropriate materials for the gate electrode 105 and the gate insulation layer 104 may be provided, for instance, by oxidation and/or deposition for the gate insulation layer 104 and by deposition of the material of the gate electrode 105, followed by advanced lithography and etch techniques in order to appropriately define the lateral dimensions of the gate electrode 105. For sophisticated applications, the gate length, which also affects the effective channel length, may be in the range of approximately 50 nm and even less for highly advanced semiconductor devices. Next, the offset spacer 107 may be formed on the basis of conformal deposition techniques and/or oxidation processes followed by an anisotropic etch process, wherein the initial layer thickness and the respective etch conditions may substantially determine the width 107T. Subsequently, an implantation process may be performed on the basis of appropriately selected parameters, such as energy and dose in order to form the substantially amorphized portion 109 down to a specific depth in the layer 102, wherein a certain amount of material of the semiconductor layer 102 may be maintained in its crystalline state, which may then act as a crystallization template in a later manufacturing stage for activating the dopants and re-crystallizing damaged areas of the semiconductor layer 102. Also, other implantation processes, such as a halo implantation, may be performed at this manufacturing stage. Furthermore, an implantation process 110 is performed to introduce the required dopant species for defining the extension regions 108E, wherein a respective offset to the gate electrode 105 may be obtained by the offset spacers 107. Since the final effective channel length, as well as the vertical extension of the respective deep drain and source regions, may have to be adjusted on the basis of an anneal process, the respective width 107T may be highly correlated to the corresponding anneal process parameters which, in turn, are related to the overall device characteristics.
For instance, the amorphized portion 109 may result in highly uniform conditions during the implantation of a respective dopant species, wherein, however, the amorphization may not extend down to the buried insulating layer 103, as previously explained. Hence, a subsequent implantation process for defining the deep drain and source regions may be substantially restricted to the amorphized portion 109, thereby requiring a corresponding adaptation of the respective diffusion activity in order to drive the resulting drain and source regions further towards the buried insulating layer 103. However, a corresponding diffusion in the depth direction is also accompanied by a corresponding diffusion in the lateral direction so that the initial offset defined by the offset spacer 107 and thus the width 107T may have to be adapted to the respective anneal parameters. Consequently, the width 107T may have to be selected greater than desirable in order to conform with the requirements of drain and source regions having an increased depth.
FIG. 1b schematically illustrates the transistor device 100 in a further advanced manufacturing stage. As shown, a further spacer element 111 may be provided to define, in combination with the offset spacer 107 and a corresponding etch stop layer 112, if provided, a spacer structure 113. The spacer structure 113 may also comprise additional individual spacer elements (not shown) depending on the respective process requirements. The spacer element 111 may be comprised of any appropriate material, such as silicon nitride, and may have a width adapted to define deep drain and source portions 108D formed by a respective implantation process 114, wherein, as previously described, respective process parameters may be selected such that the deep drain and source regions 108D, as implanted, may be defined within the portion 109, thereby providing highly uniform implantation conditions due to the reduction or avoidance of channeling effects. For driving the deep drain and source regions 108D towards the buried insulating layer 103, the corresponding lateral diffusion may also have to be accommodated by the spacer width 111W as is also previously explained with reference to the offset spacer 107. Thus, the overall width of the spacer structure 113 may be correlated with the overall configuration of the drain and source regions 108 comprising the extension region 108E and the deep drain and source region 108D, wherein the spacer width 111W and the thickness 107T may also be correlated in order to obtain a desired effective channel length after a corresponding anneal process.
FIG. 1c schematically illustrates the transistor device during a corresponding anneal process 115, which may be a conventional RTA process wherein respective process parameters, that is, the effective anneal temperature and the duration of the process, may be selected such that desired lateral and vertical profiles of the drain and source regions 108 are obtained. As indicated, if the drain and source regions 108 are to be extended substantially down to the buried insulating layer 103, moderately high anneal temperatures, in combination with relatively long process times, may be required, thereby also necessitating an increased width of the spacer structure 113 in order to obtain a desired effective channel length 106L. Consequently, for highly sophisticated applications, the required width of the spacer structure 113 may not allow further reduction of the overall length dimension of the transistor 100, when an increased depth of the drain and source regions 108 is required. On the other hand, using highly advanced anneal techniques, such as laser-based or flash lamp-based processes with extremely short anneal times, may not efficiently allow the increase of the drain and source regions 108 in the depth direction and may therefore require additional measures to obtain the desired effective channel length 106L and an increased vertical extension of the drain and source regions 108. For instance, the deep drain and source regions 108D may be formed prior to defining the extension regions 108E, wherein a respective anneal process may be performed to obtain a high diffusion activity. Thereafter, the respective extension regions may be defined by a corresponding implantation process followed by an anneal process with significantly reduced diffusion activity, as may be accomplished on the basis of the above-specified advanced anneal techniques. In this case, however, several additional process steps may be required, such as the removal of the spacers, forming additional spacer elements during the subsequent processing after defining the drain and source regions and the like. Hence, in view of the situation described above, advanced techniques may be desirable for improving the transistor characteristics while not unduly contributing to process complexity.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.